Nonvolatile memory circuits have been widely used in various circuit applications including computer memory, automotive applications, FPGAs (field programmable gate arrays), communication equipment, video games, code storage memories, serial configuration memories, and individual fuse bits for ID, trimming, and other post-fab SoC customization needs. The MOS (Metal-Oxide-Semiconductor) devices, which are the current basis of Ultra-Large-Scale Integration circuits such as memory circuits, are beginning to show fundamental limits associated with the laws of quantum mechanics and the limitations of fabrication techniques.
In MOS structures, the gate insulator, which is formed by an oxide layer, endures high electric fields during operation. This stress causes several detrimental physical effects such as the trapping of charges in the oxide bulk, creation of interface states, and eventually soft or hard breakdown. These phenomena affect the MOS characteristics and cause degradation of MOS parameters. Therefore, the voltage levels a gate is subjected to and the duration and the frequency of such voltages are directly proportional to the stress they exert on the device and the damages they produce.